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19-2270; Rev 0; 1/02
10-Bit, Low-Power, 2-Wire Interface, Serial, Voltage-Output DAC
General Description
The MAX5811 is a single, 10-bit voltage-output digital-toanalog converter (DAC) with an I2CTM-compatible 2-wire interface that operates at clock rates up to 400kHz. The device operates from a single 2.7V to 5.5V supply and draws only 100A at VDD = 3.6V. A low-power powerdown mode decreases current consumption to less than 1A. The MAX5811 features three software-selectable power-down output impedances: 100k, 1k, and high impedance. Other features include an internal precision Rail-to-Rail(R) output buffer and a power-on reset (POR) circuit that powers up the DAC in the 100k power-down mode. The MAX5811 features a double-buffered I2C-compatible serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5811 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device when an address mismatch is detected. The MAX5811 is specified over the extended temperature range of -40C to +85C and is available in a space-saving 6-pin SOT23 package. Refer to the MAX5812 data sheet for the 12-bit version. o Ultra-Low Supply Current 100A at VDD = 3.6V 130A at VDD = 5.5V o 300nA Low-Power Power-Down Mode o Single 2.7V to 5.5V Supply Voltage o Fast 400kHz I2C-Compatible 2-Wire Serial Interface o Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers o Rail-to-Rail Output Buffer Amplifier o Three Software-Selectable Power-Down Output Impedances 100k, 1k, and High Impedance o Read-Back Mode for Bus and Data Checking o Power-On Reset to Zero o Miniature 6-Pin SOT23 Package
Features
MAX5811
Ordering Information
PART MAX5811LEUT-T MAX5811MEUT-T MAX5811NEUT-T MAX5811PEUT-T TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 6 SOT23-6 6 SOT23-6 6 SOT23-6 6 SOT23-6 TOP MARK AAYS AAYU AAYW AAYY
Applications
Digital Gain and Offset Adjustments Programmable Voltage and Current Sources Programmable Attenuation VCO/Varactor Diode Control Low-Cost Instrumentation Battery-Operated Equipment
Functional Diagram appears at end of data sheet. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. I2C is a trademark of Philips Corp.
Typical Operating Circuit
VDD C SDA VDD SCL RP RP RS SCL RS SDA
MAX5811
Pin Configuration
TOP VIEW
VDD OUT
VDD 1 GND 2 SDA 3
6
OUT ADD SCL
MAX5811
5 4
RS SCL RS SDA
MAX5811
VDD
SOT23
OUT
________________________________________________________________ Maxim Integrated Products
1
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC MAX5811
ABSOLUTE MAXIMUM RATINGS
VDD, SCL, SDA to GND ............................................-0.3V to +6V OUT, ADD to GND ........................................-0.3V to VDD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 6-Pin SOT23 (derate 9.1mW above +70C).................727mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.) (Note 1)
PARAMETER STATIC ACCURACY (Note 2) Resolution Integral Nonlinearity Differential Nonlinearity Zero-Code Error Zero-Code Error Tempco Gain Error Gain-Error Tempco DAC OUTPUT Output Voltage Range DC Output Impedance Short-Circuit Current Wake-Up Time DAC Output Leakage Current DIGITAL INPUTS (SCL, SDA) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (SDA) Output Logic Low Voltage Three-State Leakage Current Three-State Output Capacitance VOL IL ISINK = 3mA Digital inputs = 0 or VDD 0.1 6 0.4 1 V A pF Digital inputs = 0 or VDD VIH VIL 0.05 x VDD 0.1 6 1 0.7 x VDD 0.3 x VDD V V V A pF No load (Note 4) Code = 200 hex VDD = 5V, VOUT = full scale (short to GND) VDD = 3V, VOUT = full scale (short to GND) VDD = 5V VDD = 3V Power-down mode = high impedance, VDD = 5.5V, VOUT = VDD or GND 0 1.2 42.2 15.1 8 8 0.1 1 VDD V mA s A GE Code = 3FF hex N INL DNL ZCE (Note 3) Guaranteed monotonic (Note 3) Code = 000 hex, VDD = 2.7V 6 2.3 -0.8 0.26 -3 10 0.5 4 0.5 40 Bits LSB LSB mV ppm/C %FS ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.) (Note 1)
PARAMETER DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Digital-to-Analog Glitch Impulse POWER SUPPLIES Supply Voltage Range Supply Current with No Load Power-Down Supply Current TIMING CHARACTERISTICS (Figure 1) Serial Clock Frequency Bus-Free Time Between STOP and START Conditions START Condition Hold Time SCL Pulse Width Low SCL Pulse Width High Repeated START Setup Time Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Fall Time STOP Condition Setup Time Bus Capacitance Maximum Duration of Suppressed Pulse Widths fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tr tf tf tSU,STO Cb tSP (Note 5) 0 (Note 5) (Note 5) (Note 5) 0 1.3 0.6 1.3 0.6 0.6 0 100 0 0 20 + 0.1Cb 0.6 400 50 300 300 250 0.9 400 kHz s s s s s s ns ns ns ns s pF ns VDD All digital inputs at 0 or VDD = 3.6V All digital inputs at 0 or VDD = 5.5V All digital inputs at 0 or VDD = 5.5V 2.7 100 130 0.3 5.5 170 190 1 A V SR To 1/2LSB code 100 hex to 300 hex or 300 hex to 100 hex (Note 5) Code = 000 hex, digital inputs from 0 to VDD Major-carry transition (code = 1FF hex to 200 hex and 200 hex to 1FF hex) 0.5 4 0.2 12 12 V/s s nV-s nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5811
Note 1: Note 2: Note 3: Note 4: Note 5:
All devices are 100% production tested at TA = +25C and are guaranteed by design for TA = TMIN to TMAX. Static specifications are tested with the output unloaded. Linearity is guaranteed from codes 29 to 995. Offset and gain error limit the FSR. Guaranteed by design. Not production tested.
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC MAX5811
Typical Operating Characteristics
(VDD = +5V, RL = 5k, TA = +25C.)
INTEGRAL NONLINEARITY vs. INPUT CODE
MAX5811 toc01
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5811 toc02
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5811 toc03
1.00 0.75 INTEGRAL NONLINEARITY (LSB) 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 256 512 INPUT CODE 768
1.25 INTEGRAL NONLINEARITY (LSB)
1.25 INTEGRAL NONLINEARITY (LSB)
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0.25
0 1024 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
MAX5811 toc04
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5811 toc05
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
MAX5811 toc06
1.00 DIFFERENTIAL NONLINEARITY (LSB) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 256 512 INPUT CODE 768
0 DIFFERENTIAL NONLINEARITY (LSB)
0 DIFFERENTIAL NONLINEARITY (LSB)
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5 1024 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V)
-0.5 -40 -15 10 35 60 85 TEMPERATURE (C)
ZERO-CODE ERROR vs. SUPPLY VOLTAGE
MAX8511 toc07
ZERO-CODE ERROR vs. TEMPERATURE
MAX5811 toc08
GAIN ERROR vs. SUPPLY VOLTAGE
MAX5811 toc09
10
10
-2.0
ZERO-CODE ERROR (mV)
ZERO-CODE ERROR (mV)
8
8
-1.6 GAIN ERROR (%FSR)
6
6
-1.2
4
4
-0.8
2 NO LOAD 0 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V)
2 NO LOAD 0 -40 -15 10 35 60 85 TEMPERATURE (C)
-0.4 NO LOAD 0 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V)
4
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5k, TA = +25C.)
DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT (NOTE 6)
MAX5811 toc11 MAX5811 toc10
MAX5811
GAIN ERROR vs. TEMPERATURE
-2.0 6 5 DAC OUTPUT VOLTAGE (V) 4 3 2 1 NO LOAD 0 -40 -15 10 35 60 85 TEMPERATURE (C) 0
DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT (NOTE 6)
MAX5811 roc12
2.5
DAC OUTPUT VOLTAGE (V)
-1.6 GAIN ERROR (%FSR)
2.0
-1.2
1.5 CODE = 100 hex 1.0
-0.8
-0.4
0.5 CODE = 3FF hex 0 2 4 6 8 10 0 0 2 4 6 8 10 OUTPUT SINK CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
SUPPLY CURRENT vs. INPUT CODE
MAX5811 toc13
SUPPLY CURRENT vs. TEMPERATURE
MAX5811 toc14
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5811 toc15
120 100 SUPPLY CURRENT (A) 80 60 40 20 NO LOAD 0 0 256 512 INPUT CODE 768
100
100
SUPPLY CURRENT (A)
SUPPLY CURRENT (A) NO LOAD CODE = 3FF hex
95
90
80
90
70
85
60 CODE = 3FF hex NO LOAD 50 35 60 85 2.5 3.5 4.5 5.5
80 1024 -40 -15 10 TEMPERATURE (C)
SUPPLY VOLTAGE (V)
POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
POWER-DOWN SUPPLY CURRENT (nA)
MAX58111 toc16
POWER-UP GLITCH
MAX5811 toc17
EXITING SHUTDOWN
MAX5811 toc18
500
400 TA = -40C TA = +25C 200 TA = +85C ZOUT = HIGH IMPEDANCE NO LOAD 0 2.7 3.4 4.1 4.8
5V VDD 0 OUT 500mV/div
300
OUT
10mV/div
100
5.5
100s/div
SUPPLY VOLTAGE (V)
CLOAD = 200pF
2s/div CODE = 200 hex
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC MAX5811
Typical Operating Characteristics (continued)
(VDD = +5V, RL = 5k, TA = +25C.)
MAJOR-CARRY TRANSITION (POSITIVE)
MAX5811 toc19
MAJOR-CARRY TRANSITION (NEGATIVE)
MAX5811 toc20
SETTLING TIME (POSITIVE)
MAX5811 toc21
5V VDD 0 OUT 5mV/div OUT 500mV/div
OUT
10mV/div
100s/div
CLOAD = 200pF RL = 5k
2s/div CODE = 200 hex to 1FF hex
CLOAD = 200pF
2s/div CODE = 100 hex to 300 hex
SETTLING TIME (NEGATIVE)
MAX5811 toc22
DIGITAL FEEDTHROUGH
MAX5811 toc23
OUT
500mV/div
CLOAD = 200pF
2s/div CODE = 300 hex to 100 hex
CLOAD = 200pF fSCL = 12kHz
CODE = 000 hex
Note 6: The ability to drive loads less than 5k is not implied.
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC
Pin Description
PIN 1 2 3 4 5 6 NAME VDD GND SDA SCL ADD OUT Power Supply and DAC Reference Input Ground Bidirectional Serial Data I/O Serial Clock Line Address Select. A logic high sets the address LSB to 1, a logic low sets the address LSB to 0. Analog Output FUNCTION
MAX5811
Detailed Description
The MAX5811 is a 10-bit, voltage-output DAC with an I 2C/SMBus-compatible 2-wire interface. The device consists of a serial interface, power-down circuitry, input and DAC registers, a 10-bit resistor string DAC, unity-gain output buffer, and output resistor network. The serial interface decodes the address and control bits, routing the data to either the input or DAC register. Data can be directly written to the DAC register immediately updating the device output, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered.
buffer output swings rail-to-rail, and is capable of driving 5k in parallel with 200pF. The output settles to 0.5LSB within 4s.
Power-On Reset
The MAX5811 features an internal POR circuit that initializes the device upon power-up. The DAC registers are set to zero scale and the device is powered-down with the output buffer disabled and the output pulled to GND through the 100k termination resistor. Following power-up, a wake-up command must be initiated before any conversions are performed.
Power-Down Modes
The MAX5811 has three software-controlled low-power power-down modes. All three modes disable the output buffer and disconnect the DAC resistor string from VDD, reducing supply current draw to 300nA. In power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1k termination resistor. In powerdown mode 2, the device output is internally pulled to GND by a 100k termination resistor. Table 1 shows the power-down mode command words. Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode.
DAC Operation
The MAX5811 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5811's input coding is straight binary, with the output voltage given by the following equation: V x(D) VOUT = REF 2N where N = 10 (bits), and D = the decimal value of the input code (0 to 1023).
Output Buffer
The MAX5811 analog output is buffered by a precision, unity-gain follower that slews at about 0.5V/s. The
Digital Interface
The MAX5811 features an I2C/SMBus-compatible 2wire interface consisting of a serial data line (SDA) and
Table 1. Power-Down Command Bits
POWER-DOWN COMMAND BITS PD1 0 0 1 1 PD0 0 1 0 1 Power-up device. DAC output restored to previous value. Power-down mode 0. Power-down device with output floating. Power-down mode 1. Power-down device with output terminated with 1k to GND. Power-down mode 2. Power-down device with output terminated with 100k to GND. MODE/FUNCTION
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC MAX5811
SDA
tSU, DAT tLOW SCL tHIGH tHD, STA tHD, DAT
tSU, STA
tHD, STA
tBUF tSP tSU, STO
tR
tF
START CONDITION
REPEATED START CONDITION
STOP CONDITION
START CONDITION
Figure 1. 2-Wire Serial lnterface Timing Diagram
a serial clock line (SCL). The MAX5811 is SMBus compatible within the range of VDD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5811 and the master at rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX5811 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX5811 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX5811 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor (500 or greater) to generate a logic high voltage (see Typical Operating Circuit). Series resistors RS are optional. These series resistors protect the input stages of the MAX5811 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see START and STOP Conditions). SDA and SCL idle high when the I2C bus is not busy.
S SCL
Sr
P
SDA
Figure 2. START/STOP Conditions
SCL SDA STOP START
LEGAL STOP CONDITION
SCL SDA
START
ILLEGAL STOP
ILLEGAL EARLY STOP CONDITION
Figure 3. Early STOP Condition
START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to-
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC
low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5811. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see Acknowledge Bit). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX5811 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Early STOP Conditions The MAX5811 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP conditions. Repeated START Conditions A REPEATED START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5811 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5811 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX5811 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7bit slave address (Figure 4). When idle, the MAX5811 waits for a START condition followed by its slave address. The serial interface compares each address
MAX5811
Table 2. MAX5811 I2C Slave Addresses
PART MAX5811L MAX5811L MAX5811M MAX5811M MAX5811N MAX5811N MAX5811P MAX5811P VADD GND VDD GND VDD GND VDD GND VDD DEVICE ADDRESS (A6...A0) 0010 000 0010 001 0010 010 0010 011 0110 100 0110 101 1010 100 1010 101
S
A6
A5
A4
A3
A2
A1
A0
R/W
Figure 4. Slave Address Byte Definition
C3
C2
C1
C0
D9
D8
D7
D6
Figure 5. Command Byte Definition
value bit by bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX5811 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX5811 issues an ACK by pulling SDA low for one clock cycle. The MAX5811 has eight different factory/user-programmed addresses (Table 2). Address bits A6 through A1 are preset, while A0 is controlled by ADD. Connecting ADD to GND sets A0 = 0. Connecting ADD to VDD sets A0 = 1. This feature allows up to eight MAX5811s to share the same bus. Write Data Format In write mode (R/W = 0), data that follows the address byte controls the MAX5811 (Figure 5). Bits C3-C0 configure the MAX5811 (Table 3). Bits D9-D0 are DAC data. Bits S1 and S0 are sub-bits and are always zero. Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data is not updated and the
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9
10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC MAX5811
Table 3. Command Byte Definitions
SERIAL DATA INPUT C3 C2 C1 C0 D9/PD1* DAC DATA D8/PD0* DAC DATA D7-D6 DAC DATA FUNCTION Load DAC with new data from the following data byte and update DAC output simultaneously as soon as data is available from the serial bus. The DAC and input registers are updated with the new data. Load input register with data from the following data byte. DAC output remains unchanged. Load input register with data from the following data byte. Update DAC output to the previously stored data. Update DAC output from input register. The device ignores any new data. Read data request. Data bits are ignored. The contents of the DAC register are available on the bus. Power up the device. Power-down mode 0. Power down device with output floating. Power-down mode 1. Power down device with output terminated with 1k to GND. Power-down mode 2. Power down device with output terminated with 100k to GND.
1
1
0
0
1 1 1 1 0 0 0 0
1 1 1 0 1 1 1 1
0 1 1 X X X X X
1 0 1 X X X X X
DAC DATA DAC DATA X X 0 0 1 1
DAC DATA DAC DATA X X 0 1 0 1
DAC DATA DAC DATA XX XX XX XX XX XX
*When C3 = 0 and C2 = 1, data bits D9 and D8 write to the power-down registers (PD1 and PD0). X = Don't care.
MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W ACK MSB C3 C2 C1 C0 D9 D8 D7 LSB D6 ACK
MSB D5 D4 D3 D2 D1 D0 S1
LSB S0 ACK P
EXAMPLE WRITE DATA SEQUENCE MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W ACK MSB C3 C2 X X PD1 PD0 X LSB X ACK P
EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE
Figure 6. Example Write Command Sequences
write cycle must be repeated. Figure 6 shows two example write data sequences.
Read Data Format In read mode (R/W = 1), the MAX5811 writes the contents of the DAC register to the bus. The direction of
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC MAX5811
MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W =0 ACK MSB C3 C2 X X X X X LSB X ACK
DATA BYTES GENERATED BY MASTER DEVICE MSB Sr A6 A5 A4 A3 A2 A1 A0 LSB R/W =1 ACK MSB X X PD1 PD0 D9 D8 D7 LSB D6 ACK
DATA BYTES GENERATED BY MAX5811
ACK GENERATED BY MASTER DEVICE
MSB D5 D4 D3 D2 D1 D0 X
LSB X ACK P
Figure 7. Read Word Data Sequence
IN
OUT VDD MAX6030/ MAX6050 GND
MAX5811
Digital Feedthrough Suppression
When the MAX5811 detects an address mismatch, the serial interface disconnects the SCL signal from the core circuitry. This minimizes digital feedthrough caused by the SCL signal on a static output. The serial interface reconnects the SCL signal once a valid START condition is detected.
OUT
GND
Applications Information
Figure 8. Powering the MAX5811 from an External Reference
data flow reverses following the address acknowledge by the MAX5811. The device transmits the first byte of data, waits for the master to acknowledge, then transmits the second byte. Figure 7 shows an example read data sequence. I2C Compatibility The MAX5811 is compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I 2 C 8-bit communications. The general call address is ignored. The MAX5811 address is compatible with the 7-bit I2C addressing protocol only. No 10-bit address formats are supported.
Powering the Device from an External Reference
The MAX5811 uses the VDD as the DAC voltage reference. Any power-supply noise is directly coupled to the device output. The circuit in Figure 8 uses a precision voltage reference to power the MAX5811, isolating the device from any power-supply noise. Powering the MAX5811 in such a manner greatly improves overall performance, especially in noisy systems. The MAX6030 (3V, 75ppm/C) or the MAX6050 (5V, 75ppm/C) precision voltage references are ideal choices due to the low power requirements of the MAX5811.
Digital Inputs and Interface Logic
The MAX5811 2-wire digital interface is I2C and SMBus compatible. The two digital inputs (SCL and SDA) load the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow-transition interfaces such as
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11
10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC MAX5811
Functional Diagram
VDD
INPUT REGISTER
MUX AND DAC REGISTER
10-BIT DAC
OUT
RESISTOR NETWORK
SERIAL INTERFACE
POWER-DOWN CIRCUITRY
MAX5811
SDA
ADD
SCL
GND
optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels.
PART
Selector Guide
ADDRESS 0010 00X 0010 01X 0110 10X 1010 10X MAX5811LEUT MAX5811MEUT MAX5811NEUT MAX5811PEUT
Power-Supply Bypassing and Ground Management
Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power-supply ground is short and low impedance. Bypass V DD with a 0.1F capacitor to ground as close to the device as possible.
Chip Information
TRANSISTOR COUNT: 7172 PROCESS: BiCMOS
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10-Bit Low Power 2-Wire Interface Serial, Voltage-Output DAC
Package Information
MAX5811
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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